1. Field of the Invention
The present invention relates to a parallel adder, and in particular, to a parallel adder that performs high speed operations.
2. Background of the Related Art
FIG. 1A is a block diagram illustrating a related art ripple carry type adder in which a carry generated by a lower full adder is inputted as an additional input signal of an upper full adder, which is adjacent the a lower full adder. As shown in FIG. 1A, in a first full adder FA10, input signals A0, B0 and a carry input signal Cin are added to output a sum signal S0. A carry signal C0 is output from the first full adder FA10 to be an input signal for a second full adder FA11. The second full adder FA11 adds input signals A1, B1, and the carry input signal C0 to output a sum signal S1. The carry signal C1 is inputted to a third full adder FA12 as an input signal. The above-described processes are performed as many times as the prescribed number of bits.
FIG. 1B is a block diagram illustrating a related art carry selection type adder. In an adder RCA21, on the assumption that there is a carry signal, an addition operation is performed. In an adder RCA22, on the assumption that there is not a carry signal, an addition operation is performed. As a result of the actual addition by an adder RCA11, the addition result of either the adder RCA21 or the adder RCA22 is selected and outputted through a multiplexor MUX. The addition result is selected based on whether the carry signal from the adder RCA11 is present.
In other words, in the adder RCA11, four bit input signals (A0, B0), (A1, B1), (A2, B2) and (A3, B3) are added to output the carry input signal Cin and four bit sum output signals S0 through S3. Additionally, in the adder RCA21, on the assumption that there is a carry signal Cin(Cin=1), four bit input signals (A4, B4), (A5, B5), (A6, B6), (A7, B7) and a carry input signal (Cin) are added to output four bit sum output signals S4 through S7. In the adder RCA22, on the assumption that there is not a carry signal Cin(Cin=0), four bit input signals (A4, B4), (A5, B5), (A6, B6), (A7, B7) and a carry input signal Cin(Cin=0) are added to output and four bit sum output signals S4 through S7.
When the actual addition is performed by the adder RCA11, the carry output signal Cout having the value xe2x80x9c1xe2x80x9d may be generated, or the carry output signal Cout may not be generated, so that the value thereof may be xe2x80x9c0xe2x80x9d. When the array output signal Cout is generated, the multiplexor MUX is controlled in accordance with the carry output signal (Cout=1), and the sum output signal of the adder RCA21 is selected and outputted. When the carry output signal Cout is not generated, the multiplexor MUX is controlled in accordance with the carry output signal (Cout=0), and the sum output signal from the adder RCA22 is selected and outputted.
FIG. 2A is a circuit illustrating a related art full adder. In FIG. 2A, when input signals A and B are both high level (i.e., a logic value of xe2x80x9c1xe2x80x9d) and a carry signal C is high level or xe2x80x9c1xe2x80x9d, an OR-gate OR1 outputs xe2x80x9c1xe2x80x9d, and an AND-gate AD1 outputs xe2x80x9c1xe2x80x9d. In addition, a NOR-gate NOR1 outputs xe2x80x9c0xe2x80x9d irrespective of the output from an AND-gate AD2. The output value xe2x80x9c0xe2x80x9d from the NOR-gate NOR1 is inverted to xe2x80x9c1xe2x80x9d by an inversion buffer B1, and the carry signal is outputted as xe2x80x9c1xe2x80x9d.
FIG. 2B is a detailed circuit diagram illustrating a related art full adder. In FIG. 2B, when input signals A and B are both xe2x80x9c1xe2x80x9d, and a carry signal C is xe2x80x9c1xe2x80x9d, PMOS transistors PM1-PM4 are turned off. Thus, xe2x80x9c0xe2x80x9d is outputted from a node N1. The outputted value xe2x80x9c0xe2x80x9d from the node N1 is inverted to xe2x80x9c1xe2x80x9d by an inversion buffer B2, and a carry signal is outputted as xe2x80x9c1xe2x80x9d.
In addition, a PMOS transistor PM9 is turned on in accordance with a value xe2x80x9c0xe2x80x9d outputted from the node N1. Since PMOS transistors PM6-PM8 and PMOS transistors PM10-PM12 are all turned off, xe2x80x9c0xe2x80x9d is outputted from common nodes N2 and N3. The outputted value xe2x80x9c0xe2x80x9d from the node N3 is inverted to xe2x80x9c1xe2x80x9d by the inversion buffer B1, and the sum is outputted as xe2x80x9c1xe2x80x9d.
FIG. 3A is a diagram illustrating an output timing of a related art ripple type adder. As shown in FIG. 3A, in a full adder FA10, input signals A0 and B0 and a carry input signal Cin are added, and a delay time of xcfx84c is generated until a carry output signal C0 is generated. In a full adder FA11, input signals A1 and B1 and a carry input signal (Cin=C0) are added, and a delay time of xcfx84c is generated until the carry output signal C1 is generated. Accordingly, a total delay time of 2xcfx84c is generated before the carry output signal C1.
Since the delay time of xcfx84c is generated from each full adder, a total delay time of 8xcfx84c is generated by an 8 bit ripple carry type parallel adder. In other words, since an addition operation is performed in order by the upper full adder after a carry output signal is generated by the preceding lower full adder, a relatively large amount of delay time (a processing time) is required.
FIG. 3B is a diagram illustrating an output timing of a related art carry selection type adder. As shown in FIG. 3B, in the RCA11, four bits input signals (A0, B0), (A1, B1), (A2, B2), (A3, B3) and a carry input signal Cin are added, and a delay time of 4xcfx84c is generated until the carry output signal Cout is generated. However, since the remaining addition operations are performed by the adders RCA21 and RCA22, a no additional delay time is required. A delay time of xcfx84c for a selection operation of the multiplexor MUX is added in accordance with a carry output signal Cout from the adder RCA11. Thus, a total delay time of 5xcfx84c is generated.
The related art adders have various disadvantages. As described above, in the ripple carry type adder, since the addition operation is performed sequentially by the upper adder after a carry output signal is generated by the lower adder, the delay time is generated proportionally to the number of output bits. In the carry selection type parallel adder, since the upper adder is arranged in parallel, it is possible to slightly reduce the delay time. In other words, when a carry output is outputted from the lower adder, a predetermined result value is selected and outputted in accordance with the actual addition operation. However, the surface of the parallel adder is necessarily increased due to a laminated structure of the system.
An object of the present invention to provide a parallel adder that overcomes at least the problems and disadvantages in the related art.
Another object of the present invention to provide a parallel adder that generates a carry signal more rapidly.
A further object of the present invention is to provide a parallel adder having a reduced size/layout.
A further object of the present invention is to provide a parallel adder that selects a pass transistor after passing a carry signal through the NAND-gate/NOR-gate to reduce a layout surface when generating a sum output signal.
Still another object of the present invention is to provide a parallel adder for a digital signal processor (DSP).
To achieve the above objects, features and/or advantages in whole or in part, there is provided a parallel adder that includes a first full adder including a logic combination unit for NORing and NANDing input signals and for generating a control signal, a buffer for inverting an inverted carry input signal in accordance with the control of the logic combination unit, a carry output unit for generating a carry signal in accordance with the control of the logic combination unit and for outputting the output signal from the buffer as a carry signal, an output controller for logically combining the output signal from the logic combination unit and for generating a control signal, and a sum output unit controlled by the sum output controller for receiving the inverted carry signal and for generating a sum output signal, and a second full adder including a logic combination unit, a buffer, and a carry output unit for receiving inverted input signals from the inverters and a carry input signal from a first full adder and for generating an inverted carry output signal, a sum output controller having the same construction as the sum output controller, and a sum output unit for receiving the carry input signal and for generating a sum output signal in accordance with the control of the sum output controller, wherein the first and second full adder are formed in a multiple structure.
The present invention may be achieved in a whole or in parts by a parallel adder including a plurality of full adders, wherein each full adder includes a logic combination unit that performs logical operations between input signals to generate a first control signal, a carry output unit receiving a carry input signal to generate a carry output signal based on the first control signal and a sum output controller for logically combining the first control signal to generate a second control signal and generating a sum output signal based on the second control signal and the carry input signal.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.